Low-Voltage Differential Signaling (LVDS) is the method of choice for transmission of video data to Liquid-Crystal Display (LCD) panels, an area of recent fast-increasing importance in consumer electronics. An LVDS video transceiver receives video data and maps it to the Red-Green-Blue (RGB) format for post-processing and resending to the LCD panel. With the advent of High-Definition Television (HDTV) systems, such transceivers are required to withstand increasingly higher operating clock frequencies, and also tolerate the spread-spectrum modulation of clock and data often required to comply with radiation emission restrictions. The former limits the tolerance to delay skewing between the different channels of the transceiver, while the later poses problems to Clock and Data Recovery (CDR) circuits that must track data during video blanking periods.
Conventionally, timing recovery is performed only on the clock link by means of a delay-locked loop (DLL) circuit, and the resulting multiphase clock is used to directly sample the data links; the timing precision provided by the DLL must then accommodate not only the delay mismatch between the links but also the timing jitter in them.
At high frequencies the precision provided by the DLL is unsatisfactory. This invention dissociates the issues of delay mismatch tolerance and jitter tolerance, yielding maximal performance in both aspects.